Language of Computer 2 part 2

EVOLUTION OF THE INTEL x86

(Backward Compatibility)

1.  8080 (1974): 8-bit microprocessor

·Accumulator, plus 3 index-register pairs

2.  8086(1978): 16-bit extension to 8080

·        Complex instruction set (CISC)

3.   8087(1980): floating-point coprocessor

·        Adds FP instructions and register stack

4.   80286(1982): 24-bit addresses, MMU

·        Segmented memory mapping and protection

5. 80386(1985): 32-bit extension (now IA-32)

·        Additional addressing modes and operations

·        Paged memory mapping as well as segments

BASIC x86 ADDRESSING MODES 

Ø  Two operands per instruction

Source/destination operand type	Second source operand
Register	Register
Register	Immediate
Register	Memory
Memory	Register
Memory	Immediate

Table above shows the arithmetic, logical, and data transfer instructions are two-operand instructions. 

There are two important differences here. The x86 arithmetic and logical instructions must have one operand act as both a source and a destination; ARM and MIPS allow separate registers for source and destination. This restriction puts more pressure on the limited registers, since one source register must be modified. The second important difference is that one of the operands can be in memory. Thus, virtually any instruction may have one operand in memory, unlike ARM and MIPS.

 Ø  Memory addressing modes

 Address in register

 Address = Rbase + displacement

 Address = Rbase + 2scale × Rindex (scale = 0, 1, 2, or 3)

 Address = Rbase + 2scale × Rindex + displacement

x86 INSTRUCTION ENCODING

a. JE EIP + displacement

             4                     4                                 8

JE

Condition

Displacement

b. CALL

              8                                                     32 

CALL

Offset

c. MOV        EBX, [EDI + 45]

           8                1         1                     8                                 8

MOV

d

w

r/m postbyte

Displacement

d. PUSH ESI

           5                     3

PUSH

Reg

e. ADD EAX, #6765

        4              3         1                                       32

ADD

Reg

w

Immediate

f. TEST EDX, #42

        7           1            8                                                        32

TEST

w

Postbyte

Immediate

Figure above shows the instruction format for several of the example instructions. 

The opcode byte usually contains a bit saying whether the operand is 8 bits or 32 bits. For some instructions, the opcode may include the addressing mode and the register; this is true in many instructions that have the form “register = register op immediate.” Other instructions use a “postbyte” or extra opcode byte, labelled “mod, reg, r/m,” which contains the addressing mode information. This postbyte is used for many of the instructions that address memory. The base plus scaled index mode uses a second postbyte, labeled “sc, index, base.”

Ø  Variable length encoding

   ·        Postfix bytes specify addressing modes

   ·        Prefix bytes modify operation

o   Operand length, repletion, locking,..

FALLACIES

Ø                     Powerful instruction means higher performance

 §  Fewer instruction required

 §  But complex instructions are hard to implement

 o   May slow down all instruction, including simple ones

 §  Compilers are good at making fast code from simple instruction

Ø                     Use assembly code for high performance

 §  But modern compilers are better at dealing with modern processors

 §  More lines of codes means more errors and less productivity

PITFALLS 

Ø                     Sequential words are not at sequential addresses

 §  Increment by 4, not 1 !

Ø                    Keeping a pointer to an automatic variable after procedure returns

 §  E.g., passing pointer back via an argument

 §  Pointer becomes invalid when stack popped

CONCLUDING REMARKS 

 There are four design principles guide of instruction sets in making that delicate balance:
1. Simplicity favors regularity. Regularity motivates many features of the MIPS instruction set: keeping all instructions single size, always requiring three register operands in arithmetic instructions, and keeping the register fields in the same place in each instruction format.

     2. Smaller is faster. The desire of speed is the reason that MIPS has 32 registers rather than many more. 

     3. Make the common case fast. Examples of making the common MIPS case fast include PC-relative addressing for conditional branches and immediate addressing for larger constant operands.

     4. Good design demands good compromises. One MIPS example was the compromise between providing for larger addresses and constants in instructions and keeping all instructions the same length.

 Layers of software/hardware

 -- Compiler, assembler, hardware

 MIPS: typical of RISC ISAs

 -- c.f. x86

Sources:- http://www.cs.colostate.edu
                  - Lecture Note Chapter 5  

Post By: AIN NASUHA BT ABDUL YAZID